Software tools are frequently used in the design of analog, mixed-signal, memory, and custom digital circuits. These are called computer-aided design (CAD) tools. In front-end design-for-yield, designers typically choose the sizes of the devices that are part of the electrical circuit, such that the maximum possible percentage of manufactured chips meet all specifications such as, e.g., gain >60 dB and a power consumption <1 mW. As such, the designers strive to maximize the overall yield or performance specifications of ECDs. An ECD design point has values for each design variable, design variables typically comprising widths and lengths for each device, resistances for resistors, and capacitances for capacitors, etc.
When choosing values for a design point, the designer must consider the effect of global process variations, local process variations, and environmental variations on the ECD. Environmental variables can include temperature and load conditions. All these effects can be simulated simultaneously in any suitable electronic circuit simulator such as, for example, a Simulation Program with Integrated Circuit Emphasis (SPICE) software.
Monte Carlo sampling is a simple and commonly-used approach to estimate overall yield of a design. In Monte-Carlo sampling, several (e.g. 50) process points are drawn from a distribution of global or local process variables, which characterize device level process variations. For each Monte-Carlo sample (a process point), one or several environmental points are simulated. A sample (process point) is feasible if it meets all performance specifications on all environmental points. Overall yield is the percentage of Monte Carlo samples that are feasible on all specifications. Similarly, Monte Carlo sampling can be used to estimate the partial yield of a design. Partial yield for a given output performance metric is the percentage of Monte Carlo samples that are feasible on the specifications for just that output performance metric.
One simple yield-aware approach for designing electrical circuits involves using Monte-Carlo sampling of the process space directly in the design loop. That is, for every candidate design, Monte-Carlo sampling is invoked to estimate the yield of the candidate design. Unfortunately, a single circuit simulation can take 1 minute or more, which means that a Monte-Carlo sampling run can easily take more than an hour. For this reason, for many circuits of interest, it is impractical to use Monte-Carlo sampling directly within a design loop (device sizing loop), whether it be a manual or an automatic design loop. Instead, Monte-Carlo sampling is typically performed late in the front-end design process, as a verification step.
“Uncontrollable” variables are variables which affect the design's performance or yield but cannot be controlled by the designer the way that design variables can be controlled. Process variables and environmental variables are uncontrollable variables. To perform yield-aware design of electrical circuits, designers often try to simplify their design problem via “corners”, a corner being a point in the space defined by the uncontrollable variables (process variables and the environmental variables). The core idea of corners-based approaches is if corners are representative of possible process and environmental variations, then achieving satisfactory performance on the corners leads to satisfactory performance and yield with respect to all possible variations. In such corner-based methods, there are typically just a few corners. Therefore, designers can quickly simulate all corners, enabling rapid design iterations against these corners. A second benefit is that corners can be used in CAD tools that do not support probability distributions, such as traditional digital timing analysis tools.
There may be other uncontrollable variables in front-end design too, such as those related to electrical circuit parasitics, aging, or layout-dependent effects. Without loss of generality, the present disclosure does not consider these variables which can typically be treated similarly to process and/or process variations.
In corner-based design of electrical circuits, a key challenge is finding corners that are representative for the ECD. That is, the challenge lies in capturing the variation bounds of the electrical circuit's performance. If the corners are not representative, then designing with them will lead to inferior electrical circuits that do not meet targets for performance or yield.
In the prior art, there are several methodologies to extract corners, and to design electrical circuits at the corners. Examples of such prior art methodologies follow.
FIG. 1 shows the most standard traditional prior art flow for corner-based design of electrical circuits. The flow of FIG. 1 can be referred to as a Process Voltage Temperature (PVT) Foundry flow. At the outset, the present flow is for an electrical circuit that has an initial set of design variables, that can be varied in order for the electrical circuit to meet certain targets. The flow starts at 101 and takes as input foundry-supplied global process corners 102 to capture global process variations. An example of such global process corners can be drawn from CMOS device models having their global process variables set to model an NMOS component, which can have fast, slow, or typical behaviors, and a PMOS component, which can also have fast, slow, or typical behaviors. The CMOS device can then be analyzed, for example, at the Fast-NMOS/Fast-PMOS (FF), Fast-NMOS/Slow-PMOS (FS), Slow-NMOS/Fast-PMOS (SF), Slow-NMOS/Slow-PMOS (SS), or Typical-NMOS/Typical-PMOS (TT) global process corners. These global process corners are designed to bracket a digital circuits' key performance characteristics of speed and power. Given the global process corners 102, the user will create PVT corners. Each PVT corner consists of a global process corner along with an environmental point. The next action is for the user to improve, at reference numeral 104 the design of the electrical circuit against the global process corners 102 by modifying the values of design variables from their initial values. The aim of action 104 is to choose design variable values such that the worst-case performances across all PVT corners are optimized, or at least such that worst-case performances meet target performance metrics (if provided at action 103).
The design at action 104 can involve changing design variables of the ECD. Feedback on an ECD's performance metrics is typically obtained via a SPICE software application or, sometimes, equations or response surface models. For each performance metric, an ECD's overall output performance is established as the worst-case performance metrics across all global process corners. Action 104 may be performed manually, or automatically (e.g., with an optimizer), or with a mix of manual design and automatic design. If the ECD's target performance metrics are known and input at action 103, then the goal of action 104 will be to change the ECD variables such that all target performance metrics are met. If the target performance metrics are not input, then the user (designer) can choose a design that has a reasonable tradeoff among circuit performances.
At action 105, the user may choose to run a Monte-Carlo sampling, to identify the overall yield of the ECD obtained at action 104. The strengths of the flow shown at FIG. 1 include designer familiarity, and simplicity because the designer does not need to determine specific corners for each new circuit design. However, this approach has several problems. First, the global process corners used in action 104 do not bracket performance characteristics other than speed and power. This is a problem in digital circuit design, and an even bigger problem in analog, radio frequency (RF), and memory design where speed and power are typically not the most important performance characteristics (metrics). Second, it ignores local process variation, which may have major effect on overall yield. Also, there is no reliable means for the user to choose environmental values to cause worst-case performance. Finally, the approach does not provide a means to design against a particular target yield.
FIG. 2 shows another prior art flow, which can be referred to as a PVT Design-specific flow. This flow starts at action 101′. At the outset, the present flow is for an electrical circuit that has an initial set of design variables, that can be varied in order for the electrical circuit to meet certain targets. As in the PVT Foundry flow of FIG. 1, it inputs FF/SS global process corners 106 and optionally inputs target performance metrics 107. But whereas the PVT Foundry flow leaves it to the user to determine environmental values at different FF/SS global process corners, the flow of FIG. 2 automatically determines, at action 108, combinations of global process corners and environmental values that bracket performances. The action 108 can be performed in several ways. A simple way is to enumerate all possible combinations of global process corners and environmental values, simulate them all (typically 50-1000 simulations), and pick the simulated corners causing worst-case performance of the electrical circuit being designed. The actions of design 109 and Monte-Carlo sampling 110 are like actions 104 and 105 of the PVT Foundry flow of FIG. 1. The flow of FIG. 2 brackets all performance characteristics, and gives a reliable means to choose environmental values to cause worst-case performance. However, the present flow ignores local process variation and does not provide a means to design against a particular target yield.
FIG. 3 shows another prior art flow which can be referred to as Statistical linear-RSM (Response Surface Modeling) flow (for example, see: Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich, “Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search,” in Proceedings Design Automation Conference, 2001, pp. 858-863). At the outset, the present flow, as in the prior art flows of FIGS. 1 and 2, is for an electrical circuit that has an initial set of design variables, that can be varied in order for the electrical circuit to meet certain targets. The flow of FIG. 3 begins at 111 and inputs the ECD's target performance metrics at action 112. The flow then performs action 113 to 117 in an iterative loop. At action 113, each input variable (global process variable, local process variable, environmental variable, and, optionally, design variable) is perturbed by a small amount to obtain perturbation points, and, the ECD is simulated at the perturbation points. Additionally, the nominal point is simulated. Action 114 takes the simulation results to construct a linear model for each performance metric of the ECD, mapping the input variables to each performance metric. Action 115 determines the process/environmental corners at which each linear model is likely infeasible, that is, determines process/environmental points at which each linear model likely fails to meet its respective target performance metric. In typical cases, there is one target performance metric for each performance, either an upper bound or a lower bound, and therefore one corner for that performance. (In some cases there are both upper and lower bounds, and therefore two corners for that performance. Without loss of generality, only one corner per performance metric can considered in the present example. The actions of design 116 and Monte-Carlo sampling 117 are like actions 104 and 105 of the PVT Foundry flow of FIG. 1. If the user is satisfied with the yield or performance 118, the design loop terminates; otherwise it repeats.
As a strength, the flow of FIG. 3 considers global process, local process, and environmental variations. Its main weakness is the assumption of a linear mapping from process and environmental variables to performance, which is very often not true, especially in modern process geometries (e.g., 45 nm features on electrical circuits). This assumption may cause the corners extracted at 115 to be far from the feasibility boundary, and therefore, the iterative design process may not converge to good designs. Also, this approach assumes that target performance metrics are provided; it does not provide a means to explore tradeoffs among problem specifications at a target yield.
FIG. 4 shows another prior art flow which can be refereed to as: “Statistical Optimal-Worst-Case” (for example, see Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L. Richard Carley, Practical Synthesis of High-Performance Analog Circuits, Kluwer Academic Publishers, Boston, Mass., 1998, ISBN 0792382374). At the outset, the present flow, as in the prior art flows described above, is for an electrical circuit that has an initial set of design variables, that can be varied in order for the electrical circuit to meet certain targets. The flow starts at 119. Optionally, target performance metrics can be provided at 120. Action 121 performs the corner extraction. Specifically, for each performance metric, action 121 finds a corner that causes the worst-case performance in a space bounded by a hypercube. The hypercube has one dimension for each global or local process variation, with minimum/maximum variations of +/−“n” standard deviations (e.g., n=3). The hypercube also has one dimension for each environmental variable. Search in this hypercube can be conducted with an optimization algorithm, or by full enumeration if the dimensionality of the hypercube is low. The actions of design 122 and Monte-Carlo sampling 123 are like actions 104 and 105 of the PVT Foundry flow of FIG. 1. The flow ends at 124 if the ECD meets the termination criteria (e.g., target performance metrics).
The main weakness of the flow of FIG. 4 is that it returns highly pessimistic corners. That is, by searching across a hypercube in process variable space, the corners of the hypercube can be very improbable (especially if there is a large number of process variables), leading to causes of failure that will likely never exist in practice. It may be very difficult to even design circuits that meet these corners, and by doing so they may trade off other more important goals. A second weakness of this flow is that, for the case when target performance metrics are given, the extracted corners obtained at action 121 do not have any direct relationship to yield.
FIG. 5 shows another prior art flow which can be referred to as a “Statistical Monte-Carlo-Worst-Case” flow. Whereas the Statistical Optimal-Worst-Case flow of FIG. 4 found worst-case corners using optimization, the flow of FIG. 5 finds worst-case corners using Monte-Carlo sampling. The benefit of this is that the same Monte-Carlo simulation data that is used for verification can be used for extracting corners. At the outset, the present flow, as in the above prior art flows, is for an electrical circuit that has an initial set of design variables (design point), that can be varied in order for the electrical circuit to meet certain targets. The flow starts at 126. Monte Carlo sampling (like 105 of PVT Foundry flow) is performed at 127. This can be termed the “verification” step. At action 128, If the ECD has adequate yield and performance, it can stop 129. Otherwise, the flow proceeds to action 130. For each performance metric, a Monte-Carlo sampled process point and an environmental point that causes the worst-case performance is selected as a corner. (Worst case is the minimum or maximum value of the performance metric, depending on the metric; for example, worst-case value for power would be maximum power. For some performance metrics, both the minimum and maximum are taken, giving two worst-case performances and two worst-case corners for that performance metric.) At action 131, the electrical circuit is designed against the corners (e.g., by modifying design variables in the ECD). The sequence of actions 127-131 until action 128 is satisfied. At each iterative loop, previous corners are typically kept as well, to prevent non-convergence. The key strength of this approach is the reuse of verification Monte-Carlo data for corner extraction. This can reduce the number of simulations required. As a further advantage, the extracted corners of the present flow are not necessarily pessimistic. The main weakness of the flow of FIG. 5 is that there is no relation between extracted corners and any pre-determined target yield or target performance metrics. Also, the present flow will likely take several iterations to hit the target yield. Combined with keeping corners from previous iterations, the design action 131 will slow down considerably in later iterations.
Therefore, improvements in corner extraction and design of electrical circuits at the extracted corners are desirable.